Design of Multi-Mode Semi-Parallel LDPC Decoders for WiMAX Standards

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Jutaphet Wetcharungsri Narong Buabthong Pakon Thuphairo Paramin Sangwongngam Keattisak Sripimanwat

Abstract

Demands for highly efficient Low-density parity check (LDPC) encoders and decoders have significantly risen in a wide range of applications, including deep-space communications, satellite modems, mobile communications, and storage. In this article, a pipelining technique was applied to an implementation of synchronous semi-parallel LDPC decoders over FPGA in order to reduce the intrinsic latency due to the fact that a shuffle network, check node, and some modules in VNP units are combinational circuits. Our technique proposed that a certain number of registers can be intentionally placed at specific stages in the conventional design, thus realizing pipeline structures. Three methods, named ‘Scheme 1’, ‘Scheme 2’, and ‘Scheme 3’, were proposed. The first method employs a single-stage exchange pipeline while the second one makes use a double-stage exchange pipeline. The third technique improves upon the second one by creating a variable node processor (VNP) update pipeline. Our proposed architecture focuses on not only an aspect of path delays in a large LDPC network but also the optimization of FPGA resources, e.g., the number of used slices. To test the performance of the proposed schemes, the simulations of the conventional design and each proposal were performed. The numerical results indicate that improvements in important parameters, i.e., clock frequency, latency, and FPGA resource utilization, can be achieved by of the methods. All of the propose techniques are capable of raising throughput and reducing latency of the design dramatically. In Scheme 3, the throughput is increased by approximately 84 percent that of the conventional technique. Furthermore, it is noteworthy that the proposed methods with additional registers have exploited unused flip-flops in the LUTs that have been already occupied, hence achieving more effective utilization of precious FPGA resources, especially when commercial aspects are considered.

Keywords: Low-Density Parity Check (LDPC) codes; latency; semi-parallel LDPC decoders; retiming; Field Programmable Gate Array (FPGA); WiMAX; IEEE 802.16e

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How to Cite
Wetcharungsri, J., Buabthong, N., Thuphairo, P., Sangwongngam, P., & Sripimanwat, K. (1). Design of Multi-Mode Semi-Parallel LDPC Decoders for WiMAX Standards. Science & Technology Asia, 20(1), 59-72. Retrieved from https://www.tci-thaijo.org/index.php/SciTechAsia/article/view/32793
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Engineering and Information Technology